Description
About the course
Professor Indranil Sengupta, a faculty from the Department of Computer Science and Engineering at the Indian Institute of Technology, Kharagpur has designed this course. The course helps you to understand the IC technology evolution, their impacts on the development of EDA tools, and also the problem-solving techniques. This course is intended to expose learners to the key themes, ideas, and techniques in producing correct/efficient/(optimal) mappings of some semantic computation onto a physical computational substrate; in practice, many of the fundamental problems are more widely applicable in engineering than simply mapping computations, but that will be our intellectual focus for this course.
This course covers in detail, the Digital Circuit Design Flow which means that if you have a digital design or a digital circuit specification, then what are the different steps that you need to follow in order to arrive at the implementation. Only digital circuits would be considered here, and no analog designs would be considered. In addition to this, the course covers a popular Hardware Description Language known as Verilog, which will be used as a vehicle in some of the future lessons. The course also covers Logic Synthesis which includes multilevel logic minimization, Technology Mapping, and High-Level Synthesis. It also covers the testability issues. Finally, the course concludes with Physical Design Automation which further includes Floorplanning, placement, and routing etc.
Learning Outcomes
After completing this course, you will be able to:
- Understand the role of design automation tools in various realms of digital/analog design.
- Understand the various concepts like compaction, placement and partitioning, floorplanning, routing, logic synthesis, verification, and analog/RF simulation.
- Understand the core methodologies that form the engine for such design automation tools.
- You will be able to teach and train others who are interested in learning and understanding the techniques for electronic design automation (EDA).
- Boost your hireability through innovative and independent learning.
Target Audience
The course can be taken by:
Students: All students who are pursuing any professional/technical degree courses related to Electronics Engineering.
Teachers/Faculties: All teachers/faculties who wish to acquire new skills or improve their efficiency in Electronic design process.
Professionals: All working professionals from the core electronics industry.
Why Learn Electronic Design and Automation?
Electronic design automation (EDA) is a term for a category of software products and processes that help to design electronic systems with the aid of computers. Today, semiconductor makers are facing projected SoC (System-on-a-Chip) development costs of $100 million at 32 nm (nanometre) and below. The field of Electronics and Electronic Design is influencing everyone’s daily routine and changing lives through its new inventions every day, thus generating immense career opportunities for students and professionals who want to contribute in this field.
Course Features
- 24X7 Access: You can view lectures as per your own convenience.
- Online lectures: 31 hours of online lectures with high-quality videos.
- Updated Quality content: Content is latest and gets updated regularly to meet the current industry demands.
Test & Evaluation
Each lecture will have a quiz containing a set of multiple choice questions. Apart from that, there will be a final test based on multiple choice questions.
Your evaluation will include the overall scores achieved in each lecture quiz and the final test.
Certification
This course is free and it has no certificate.
Topics to be covered
- EDA Lecture-1 Introduction
- What is the Digital Circuit Design Flow and Digital Design Process?
- What is the design flow and what are the new CAD tools used?
- What are the two popular HDLs used and what is the Simplistic View Of Design Flow?
- What are the various design representations and what is the Behavioral Representation and its example?
- What are Structural Representation and its example?
- What are Physical Representation and its example?
- EDA Lecture-2 Verilog: Part-I
- What is Verilog Hardware Description Language?
- What is the concept of Verilog ""Module"" and what is the basic syntax of Module definition?
- How to specify connectivity, and what are variable data types and Net data type?
- What is a Register data type and how to specify Constant values?
- EDA Lecture-3 Verilog: Part-II
- What are the Parameters?
- What are Logic Values, Primitive Gates and how Primitive Tri-State gates are instantiated?
- What are some important points to note and what are the various Hardware Modeling Issues?
- How will the synthesis system generate a wire for f1?
- What are the various Verilog Operators?
- EDA Lecture-4 Verilog: Part-III
- What are the different description Styles in Verilog?
- What is the Continuous Assignment Data-flow Style?
- What is the Procedural Assignment Behavioral Style?
- What is the basic syntax of ""always"" block and what are the various sequential statements in Verilog?
- What are the examples of combinational and sequential logic (part - 1)?
- What are the examples of combinational and sequential logic (part - 2)?
- EDA Lecture-5 Verilog: Part-IV
- What are Blocking and Non-blocking Assignments and their different aspects?
- What are the important rules to be followed?
- What is an Up-down counter (synchronous clear) and what is the Parameterized design of an N-bit counter?
- What is a Ring Counter?
- What are Loop Statements and how to model memory and its examples?
- EDA Lecture-6 Verilog: Part-V
- How to model Finite State Machines (FSMs)?
- What are Moore Machine and its example?
- What are a Serial Parity Detector and Mealy Machine and its example?
- How to design a Sequence detector for pattern '0110'?
- What are the different examples with respect to the module?
- What is a Top level module?
- EDA Lecture-7 Verilog: Part-VI
- How to model memory and its example?
- How to Initialize memory and its example?
- What are the different specific examples of Memory Modeling?
- What is a Verilog Test Bench and how to write a Testbench and its example?
- What is the more complete version of its example?
- EDA Lecture-8 Synthesis: Part-I
- What is the Y diagram?
- What is a Logic Design and Simulation?
- What are Simulation Objectives and what is Logic Synthesis?
- What are the special considerations and what is technology mapping, its example and what is logic verification?
- EDA Lecture-9 Synthesis: Part-II
- What is the basic problem of Logic Design and how to specify Logic behavior?
- What is Logic Synthesis Problem and what is Two-level Minimization method?
- What is Espresso package and how it works?
- What are the different loop operations in Espresso?
- What is Espresso all about?
- EDA Lecture-10 Synthesis: Part-III
- What is Multilevel Logic Minimization and Optimization?
- What is Local Optimization Technique and AND/OR, NAND(NOR) transformations?
- What is Global Optimization Technique, its example an algorithm?
- What is Multilevel Logic Interactive Synthesis System, its basic concept and Global Optimization Approach?
- How is the approach illustrated with the help of examples?
- How to use common subexpressions and what is the problem of Area, Delay and Power?
- EDA Lecture-11 Synthesis: Part-IV
- How to represent Boolean Functions and what is a Binary Decision Diagram (BDD)?
- What is Shannon's Expansion?
- How to construct BDD?
- What are the various reduction rules to be followed?
- What are the benefits of BDD and how BDD is used in Synthesis?
- How functions are realized and how functional decomposition is done using MUX?
- EDA Lecture-12 Synthesis: Part-V
- What is Design Representation what is the Scope of High-Level Synthesis?
- What is Simple Transformation?
- What is Transformation with Control/Data Flow?
- How transformation is explained with the help of another example and what is compiler transformation?
- What is Constant Folding, Redundant Operator Elimination and Tree Height Transformation?
- What is Control Flattering, Logic Level and RT Level Transformation?
- EDA Lecture-13 Synthesis: Part-VI
- What is High-Level Synthesis and why it is required?
- What is Component and Behavioral Partitioning?
- What are the different partitioning techniques and what is Random Selection and Cluster Growth?
- What is Hierarchical Clustering?
- What is the Min-Cut (Kernighan-Lin) algorithm, its example and drawbacks?
- What is Goldberg-Burstein algorithm, its example and what is Simulated Annealing?
- EDA Lecture-14 Synthesis: Part-VII
- What is High-Level Synthesis, Scheduling and how to solve 2nd order differential equations(HAL)?
- What are the different Scheduling Algorithms (ASAP and ALAP)?
- What is Resource Constrained Scheduling what is the basic idea behind List-Based Scheduling?
- Time-Constrained Scheduling and its example?
- EDA Lecture-15 Backend Design: Part-I
- What is the VLSI design cycle?
- What is Physical Design and what are the different VLSI Design Styles?
- What are Field Programmable Gate Array (FPGA) and its different aspects?
- What is Gate Array and what are the characteristics of the Cells?
- What is the layout for Standard Cell, its Floorplan and what is full custom design?
- EDA Lecture-16 Backend Design: Part-II
- What is Circuit Partitioning and how it is done at different levels?
- What are the different delays in a chip and how partitioning algorithms are classified?
- What are Group Migration Algorithms, what is the extension of K-L Algorithm and what are unequal sized elements?
- Simulated Annealing and Evolution and The Annealing Curve and Simulated Annealing Algorithm
- What is the SCORE function and Performance Driven Partitioning?
- EDA Lecture-17 Backend Design: Part-III
- What are the Problem Definition and its example?
- What are the Design Style Specific Issues and how to estimate the Cost of a Floorplan?
- What are a Slicing Structure and its various aspects?
- What is a Hierarchical Floorplan and what are the various Floorplanning Algorithms?
- What is Integer Linear Programming (ILP) formulation (Part - 1)?
- What is Integer Linear Programming (ILP) formulation (Part - 1)?
- EDA Lecture-18 Backend Design: Part-IV
- What is Rectangular Dual-Graph Approach?
- What is a Rectangular Floorplan and its Dual Graph?
- What are the drawbacks of Rectangular Floorplan and what is the Hierarchical approach?
- What are the Bottom-Up Hierarchical approach and its example?
- What are a Top-Down Hierarchical approach and simulated annealing and its examples?
- EDA Lecture-19 Backend Design Part-V
- What are Simulated Annealing and its algorithm?
- How Is Simulated Annealing explained with the help of an example?
- What is Pin Assignment?
- What is Gate Array, its problem formulation, what are the design style specific issues and how algorithms are classified?
- What are Concentric Circle Mapping and Topological Pin Assignment and its examples?
- What are the Nine Zone method and Channel Pin assignment?
- EDA Lecture-20 Backend Design Part-VI
- What is Placement?
- What is the Placement Problem and how it occurs at different levels?
- How the placement problem is formulated and what are different interconnection topologies?
- How to estimate the wavelength and model Multi-terminals Nets and its examples?
- What are the Design Style Specific Issues and how Placement Algorithms are classified?
- What is the Simulated Annealing algorithm and how the TimberWolf algorithm works?
- EDA Lecture-21 Backend Design Part-VII
- What is Simulated Evolution/ Genetic Algorithm?
- What are Crossover, Mutation and Select Operators?
- What is the concept of Force-Directed Placement and its example?
- How Force Directed Approach is implemented for Constructive Placement and what is Breuer's Algorithm?
- What are Terminal Propagation and Cluster Growth Algorithms?
- What is Performance Driven Placement?
- EDA Lecture-22 Backend Design Part-VIII
- What are Routing and general routing problems?
- What is the concept of Grid Routing?
- What are the various Grid Routing Algorithms and what are Maze Running and Lee's Algorithms?
- What are the different phases of Lee's algorithm?
- How to calculate Memory Requirements in Lee's algorithm?
- How to reduce the running time and connect Multi-point Nets in Lee's Algorithm?
- EDA Lecture-23 Backend Design Part-IX
- What is a concept behind Hadlock's Algorithm and what are its advantages?
- What are Line Search and Mikami-Tabuchi's Algorithm?
- What is Hightower's Algorithm?
- What are the Steiner trees and Steiner Trees Based Algorithms?
- What is the basic idea behind Global Routing?
- What is the concept of Routing Regions and what are the different types of Channel Junctions?
- What is the Design Style Specific Issues in Global routing?
- EDA Lecture-24 Backend Design Part-X
- What Graph models are used in Global Routing and what is the Grid Graph Model?
- What is the CheckerBoard Model?
- What is the Channel Intersection Graph model?
- What are the different approaches to Global Routing and what are Sequential and Hierarchical approaches?
- What is Integer Linear Programming approach?
- What is Performance Driven Routing?
- EDA Lecture-25 Backend Design Part-XI
- What is the concept of Detailed Routing?
- What are Channels and Switchboxes and how to determine the order of Routing Regions?
- What are the Routing Considerations?
- What are Routing Models?
- What are Channel Routing and its aspects?
- What is Horizontal and Vertical Constraint Graph (HCG & VCG) and what is Two-Layer Channel Routing?
- What is the basic Left Edge Algorithm?
- EDA Lecture-26 Backend Design Part-XII
- What are Dogleg Router and its example?
- What is the Dogleg Router Cycle in VCG and its Algorithm?
- What is Net Merge Channel Router and how does it work?
- What is the Zone Representation?
- What is Net Merging and Track Assignment?
- EDA Lecture-27 Backend Design Part-XIII
- What is the basic concept behind Greedy Channel routing?
- What is Greedy Channel Router algorithm and heuristics used in it?
- How is the Greedy Channel Router algorithm illustrated with the help of an example?
- What is the Three Layer Channel and HVH Routing?
- What is Track Ordering graph?
- What is an optimal scheduling solution and Switchbox Routing?
- EDA Lecture-28 Backend Design Part-XIV
- What is the Concept of Clock Routing?
- What are the different Clocking Schemes
- What are the various Clock Buffering Mechanisms?
- What are the different Clock Routing Algorithms?
- What is the Method of Means and Medians?
- What are Zero Skew Clock and Power and Ground Routing and its different approaches?
- EDA Lecture-29 Backend Design Part-XV
- What is the concept behind Over-The-Cell (OTC) Routing?
- What are the Basic Steps in OTC Routing?
- What is Layout Compaction and Constraint Graph-Based Compaction?
- What is Shadow Propagation Method and Virtual Grid Based Compaction?
- What is 2- Dimensional Compaction and its example?
- What are 1.5 Dimensional Compaction and its example?
- EDA Lecture-30 Testing-Part-I
- Why is Testing required?
- How Verification differs from Testing and what are the different levels of Testing?
- What are the Costs associated with Testing and what is the basic Testing principle?
- Why there is a need for Fault modeling and what are the common Fault Models?
- What are Stuck-at Faults and what is Single Stuck-at Fault and its example?
- What is Fault Equivalence technique to reduce faults?
- What is Fault Dominance technique to reduce faults?
- EDA Lecture-31 Testing Part-II
- What are the multiple Stuck-at and Transistor (Switch) Faults?
- EDA Lecture-32 Testing Part-III
- What is Concurrent Fault Simulation?
- What Data structure is used, its advantages and limitations?
- What is the basic idea behind test generation, its need an algorithm?
- What are Path Sensitization and its steps?
- What is Random Pattern Testing?
- How Functional ATPG differs from Structural ATPG?
- What is Functional ATPG and Structural Test?
- EDA Lecture-33 Testing Part-IV
- What is the Design for Testability (DFT) and Ad-Hoc DFT Methods?
- What is the basic concept behind Structured Design, what is Scan Design and its Rules?
- What is Scan Flip-flop (master-slave) and how to add Scan Structure?
- How to test Scan Register?
- What are Multiple Scan Registers and what is Scan Overhead?
- What is Hierarchical Scan?
- What is Automated Scan Design and what are the different methods for selection of Scan Flip-Flop?
- EDA Lecture-34 Testing Part-V
- What is Built-in Self-Test (BIST) and what are various test Problems Alleviated by BIST?
- What are the costs Involved in BIST?
- What is Built-in Logic Block Observer?
- How to generate a Pseudo Random Pattern?
- What is an LFSR Variant (Internal-XOR Based) and what is Characteristic Polynomial?
- What are the examples of Primitive Polynomials and what is Weighted Pattern Generator?
- EDA Lecture-35 Testing Part-VI
- What is Response Compaction, its definitions and Signature Analysis?
- What is LFSR for Response Compaction
- What is the probability of Aliasing?
- What are Multiple-Input Signature Register and how to do self-testing using MISRand Parallel SRSG (STUMPS)?
- What are the benefits of BIST and what is the Testability Standard?
- What is System Test Logic and how to load Instruction Register with JTAG?
- What is Serial and Parallel Board MCM Scan and what are Tap Controller Signals?
Note : Parts of this material has been sourced from NPTEL, adapted and modified to adhere to our Pedagogical requirements and uploaded to YouTube for reuse under the same license.
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