Description

About the course

This course will provide an overview of the Verilog hardware description language (HDL) and its use in programmable logic design. The emphasis is on the synthesis constructs of Verilog HDL; however, you will also learn about some simulation constructs. You will gain a basic understanding of Verilog HDL that will enable you to begin creating your design. In this course, you will learn about design, test, and implementation of digital hardware, the hierarchy, and modeling of structures, syntax, lexical conventions, data types and memory, behavioral and register transfer level modeling. You will also learn to write RTL Verilog code for synthesis, understand gate level modeling. Also, you will learn the concept of delays, test benches, timing checks, etc. This is completely an online course which is available worldwide.

Learning Outcomes

After completing this course, you will be able to:

• Design, simulate and synthesize and computer hardware with Verilog.
• Design combinational and sequential logic that works.
• Understand Verilog hardware description language (VHDL) and its use in programmable logic design.
• Synthesize logic and state machines using automatic logic synthesis program.
• Implement state machines using Field-Programmable Gate Arrays.
• Run a timing simulation using Verilog libraries.
• Evaluate testability using fault simulation methods
• Boost your hireability through innovative and independent learning.

Target Audience

The course can be taken by:

Students: All students who are pursuing professional graduate/post-graduate courses related to computer science and engineering or data science.

Teachers/Faculties: All computer science and engineering teachers/faculties.

Professionals: All working professionals from computer science / IT / Data Science domain.

Why learn Verilog?

Verilog is a hardware description language (HDL) used to model electronic systems. Verilog is most commonly used in the design, verification, and implementation of digital logic chips at the Register transfer level (RTL) level of abstraction. Knowledge of VHDL offers exciting growth opportunities for engineers. There is a requirement of a large number of engineers in the embedded systems development and board-level hardware design.

Course Features

• 24X7 Access: You can view lectures as per your own convenience.
• Online lectures: 5 hours of online lectures with high-quality videos.
• Updated Quality content: Content is latest and gets updated regularly to meet the current industry demands.

Test Evaluation

There will be a final test containing a set of multiple choice questions. Your evaluation will include the scores achieved in the final test.

Certification

This course is free and it has no certificate.

Topics to be covered

1. Module - 1 Verilog: Part-I
   • What is Verilog Hardware Description Language?
   • What is the concept of Verilog ""Module"" and what is the basic syntax of Module definition?
   • How to specify connectivity and what are variable data types and Net data type?
   • What is a Register data type and how to specify Constant values?
2. Module - 2 Verilog: Part-II
   • What are the Parameters?
   • What are Logic Values, Primitive Gates and how Primitive Tri-State gates are instantiated?
   • What are some important points to note and what are the various Hardware Modeling Issues?
   • How will the synthesis system generate a wire for f1?
   • What are the various Verilog Operators?
3. Module - 3 Verilog: Part-III
   • What are the different description Styles in Verilog?
   • What is the Continuous Assignment Data-flow Style?
   • What is the Procedural Assignment Behavioral Style?
   • What is the basic syntax of always block and what are the various sequential statements in Verilog?
   • What are the examples of combinational and sequential logic (part - 1)?
   • What are the examples of combinational and sequential logic (part - 2)?
4. Module - 4 Verilog: Part-IV
   • What are Blocking and Non-blocking Assignments and their different aspects?
   • What are the important rules to be followed?
   • What is an Up-down counter (synchronous clear) and what is the Parameterized design of an N-bit counter?
   • What is a Ring Counter?
   • What are ""Loop"" Statements and how to model memory and its examples?
5. Module - 5 Verilog: Part-V
   • How to model Finite State Machines (FSMs)?
   • What are Moore Machine and its example?
   • What are a Serial Parity Detector and Mealy Machine and its example?
   • How to design a Sequence detector for pattern '0110'?
   • What are the different examples with respect to the module?
   • What is a Top level module?
6. Module - 6 Verilog: Part-VI
   • How to model memory and its example?
   • How to Initialize memory and its example?
   • What are the different specific examples of Memory Modeling?
   • What is a Verilog Test Bench and how to write a Testbench and its example?
   • What is the more complete version of its example?
7. Getting started with Verilog - Final Quiz